Method and device for the display of several radar images in a single mosaic

ABSTRACT

The object of the invention is a device to display several radar images in a single resultant image, formed by a mosaic image of different radar images. To this effect, the invention provides for the use of means for mutual exclusion of the radar images so that a given point of the resultant image corresponds to the display on one and only one radar.

BACKGROUND OF THE INVENTION

The present invention concerns the display of radar images and, moreparticularly, a case where one and the same geographical zone is coveredby several radars and where it is desired to obtain a single resultantimage, formed by a mosaic of the images given by the different radars.

The need to make a mosaic arises notably when the position of a radar issuch that it cannot cover the entire zone it is entrusted withmonitoring, owing to obstacles such as mountains or tall buildingscreating a shadow in the zone under surveillance, namely a sectorwithout echo. This, for example, is often the case with airportsurveillance radars.

To cover the entire zone, one or more additional radars are then needed,and are arranged so as to reach the shaded sectors of the first radar.

To enable an operator to have a comprehensive image of the zone on asingle screen, it is then necessary to make a mosaic of images given bythe different radars.

There are known ways to make this mosaic by taking, for each of thepixels of the resultant image, a video signal equal to a function (mean,maximum etc.) of each of the pixels given by the different radars.Since, in general, the images given by the different radars overlap oneanother, two types of zones are then distinguished on the single screen:

those reached by a single radar;

those reached by several (at least two) radars.

In the second type of zone, the echos of the detected objects (aircraftfor example) processed by each of the radars should, of course, besuperimposed on the screen and, to a given aircraft, there shouldtherefore. This requiremement may not necessarily be achieved due to theasynchronism of the rotation of the radars. There may be movement by theaircraft between the instant when it is detected by the first radar andthe instant when it is detected by the second one.

Furthermore, the radar video signal always contains a certain degree ofnoise and, with this type of system, the noises get added together inthe zones common to several radars.

SUMMARY OF THE INVENTION

The present invention is aimed at forming a mosaic from a plurality ofradar images, which avoids the previous drawbacks through the use ofmeans for the mutual exclusion of the radar images. To a given point ofthe resultant image, there thus corresponds the display of one and onlyone radar.

Other objects, particular features and results of the invention willemerge from the following description, illustrated by the appendedfigures.

DESCRIPTION OF THE FIGURES

FIG. 1, the block diagram of a standard digital converter of images;

FIG. 2, a first embodiment of the mosaic according to the invention;

FIG. 3, a second embodiment of the mosaic according to the invention;

FIG. 4, the block diagram of a digital converter of images comprising anancillary memory called a block memory;

FIG. 5, a third embodiment of the mosaic according to the invention;

FIG. 6, the detail of one of the elements of the previous figure;

FIG. 7, a fourth embodiment according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In these different figures, the same references pertain to the sameelements.

FIG. 1 represents a standard digital converter of images.

It will be recalled that a converter of this type, also called an IDC,has the essential role of converting a radar image, given in polarcoordinates and having relatively slow refreshing, into a televisiontype light image, enabling it to be exploited in an illuminatedenvironment.

The IDC thus receives, firstly, video signals from the radar receiverand, secondly, the radar antenna rotation signals.

The video signals are formed, firstly, by a synchronization signalindicating that a pulse has been emitted by the radar and, secondly, bythe video proper, consisting of all the responses to (echos from) thispulse. These video signals are received by an input interface 1comprising chiefly circuits for sampling the input analog informationand a memory enabling the memorizing of the video informationcorresponding to each radar pulse.

The rotation signals are formed, firstly, by a North signal which is abeep given by each passage of the antenna through the North and,secondly, by an angle increment signal indicating that the beam hasrotated by 1/nth of a turn with respect to the preceding increment if nincrements correspond to 360 degrees. These rotation signals arereceived by a set 3 of coordinates conversion circuits.

The IDC also has a memory 4, called an image memory containing, indigital form, the image which will be displayed in television mode onthe screen of a display device 6. The capacity of the memory 4 isadapted to the television standard used, i.e. it comprises as manymemory compartments as the image displayed on the screen has pixels.Furthermore, the luminance of each pixel is encoded by means of acertain number of bits. The stages for reading the content of the memory4, designed for the screen 6, and for writing the radar information,given by the interface 1 (through the block 2),in this memory areasynchronous. The reading takes priority and, during a reading stage,the writing is stopped.

The coordinates conversion set 3 thus provides for the addressing, inwriting mode, of the image memory 4 and the interface 1, through theblock 2, provides the video information to be memorized in synchronismwith the addressing.

A set 5 of television mode reading circuits provides for the addressingin reading mode of the image memory 4.

The IDC also has a set 2 of artificial remanence circuits which have therole of creating, for the digital information contained in the memory 4,for which there are no modifications due to ageing, a remanence effectcomparable to the one produced in a remanent tube where the brillianceof a dot starts decreasing as soon as it is recorded.

The IDC also has a control processor (not shown) receiving both thevideo signals and the rotation signals and providing for the control andsynchronization of all the preceding circuits.

FIG. 2 represents a first embodiment of the producing mosaic imagesaccording to the invention, in the case of two radars for example.

This figure therefore schematically represents two radars giving videoand rotation signals to two IDCs respectively. Each of the IDCs isformed by the above-described sets 1 to 5. The sets of the radar 10 IDCsbear an index a to distinguish them from those of the radar 10 IDCs.

The output video signal of each of the image memories (4, 4a) istransmitted to the display device 6 only after going through an AND typevalidation logic circuit (71, 71a) and a summator device 72, connectingthe outputs of the circuits 71 and 71a.

Each of the IDCs further has a memory called a mosaic map (70, 70a).

This mosaic map contains, for each pixel, one validation bit which,through the AND circuit (71, 71a), authorizes or does not authorize thetransmission of the content of the image memory (4, 4a) to the displaydevice 6. In the case of two radars, as shown in FIG. 2, the mosaic mapof the radar 10a is of course complementary to the mosaic map of theradar 10.

The memories containing the mosaic maps may be read-only memories,programmable if necessary, or RAMs, the content of which is loaded bythe processor of the IDC through action by the operator.

FIG. 3 shows a second embodiment of the radar for producing mosaicimages according to the invention, wherein the mosaic maps come intoplay no longer at the output of the image memories but at the level ofthe remanence sets.

This figure again shows, by way of example, the two radars 10 and 10a,the receivers and the antennas of which give the video and rotationsignals to the IDCs formed by the sets 1 to 5 (1a to 5a for the radar10a).

In this embodiment, again, with each IDC there is associated a mosaicmap, how referenced 77 and 77a respectively, but this map gives itsvalidation information to the remanence set 2 (and 2a respectively).This set further receives, as earlier, the incident video signal givenby the interface 1 and the previously recorded video signal given by theimage memory 4.

The working of the remanence circuits is standard, except with respectto the validation by the information contained in the mosaic map (77,77a).

It is recalled that the remanence set usually consists of a RAM, whichreceives the incident video signal on i bits, the memorized video signalin the image memory is provided on j bits, and gives at an output,towards the image memory, a video signal on j bits representing apredefined function of the two video signals received. Such an operationis described, for example, in the French patent application No. 82.17984filed on behalf of THOMSON-CSF.

In the case of FIG. 3, the remanence memory (2, 2a) takes an additionalinput coming from the mosaic map (77, 77a) on one bit (the validationbit), the output of this memory, always designed for the image memory(4, 4a) being then a function of the two input video signals as well asof the mosaic validation bit. In other words, using this embodiment istantamount to considering the mosaic as a particular relationship ofremanence.

This embodiment has the advantage, as compared with the previousembodiment, of avoiding the validation logic (71, 71a).

The size of the memory forming the mosaic map may be one bit per pixelIt may be smaller, in considering the pixels in the image memory byblocks, for each of which the mosaic bit is the same; in the case ofblocks of 4×4 pixels, for example, the size of the mosaic map is thusreduced by a factor of 16.

FIG. 4 is the block diagram of an IDC comprising an intermediate memorycalled a block memory.

This figure again shows the same elements as in FIG. 1, except asregards a memory 8, called a block memory, placed between the incidentvideo signal and the image memory or, more precisely, between theinterface 1 and the remanence set 2.

The organization of this intermediate memory is of the same type as thatof the image memory 4, but the adjacent pixels are furthermore assembledin boxes blocks, and these blocks are transferred in parallel into theimage memory when they are totally filled up, which makes it possible toreduce the writing load of the latter. A structure such as this isdescribed, for example, in the document No. EP. 68.852.

The structure of the block memory may be identical to that of the imagememory. In one variant embodiment, the structure of the block memory andits mode of being filled may be optimized in order to reduce the size ofthe block memory as described, for example, in the French patent No.86.01377.

The diagram of FIG. 1 is then modified in that the coordinatesconversion set also provides the addressing of the block memory inwriting and reading modes.

FIG. 5 represents a third embodiment of the mosaic according to theinvention in the case of IDCs provided with a block memory.

This figure therefore again shows the radars 10 and 10a, each connectedto the sets 1, 3, 8 and 1a, 3a, 8a respectively, described in FIG. 4,the sets 4, 5 and 6 being common to both radars, as well as theremanence set referenced herein as 20.

The device of FIG. 5 further comprises an arbitrator circuit 73 whichhas the function of authorizing the reading of either of the blockmemories 8 and 8a, given that the outputs of these two memories areconnected to one and the same input of the remanence set 20. Thiscircuit 73, alternately and in a predefined manner, authorizes thereading of one memory and then of the other, and it accompanies thisauthorization of reading by an identification of the radar which is thusauthorized to provide its pieces of information to the set 20. Thisidentification may consist, for example, of a number.

The system of FIG. 5 also has a memory 74, containing a single mosaicmap, also provided to the remanence set 20.

An embodiment of the set 20 is described in greater detail in FIG. 6.

The set 20 is formed by the preceding remanence memory 2, preceded by avalidation logic circuit which comprises a comparator 21 and an ANDcircuit 22. The mosaic map contains herein, for each pixel, theidentification of the radar to be taken into account. Thisidentification is provided to the comparator which further receives,from the arbitrator circuit 73, the identification of the radar nogiving the video signal. The comparator 21 delivers a validation signalif the identification of the radar corresponds to the one authorized bythe mosaic map. The validation signal is given to the AND circuit 22which furthermore receives the video signal and transmits it in theevent of validation to the remanence memory 2.

Another embodiment of the set 20 consists in proceeding in a way similarto that described above with reference to FIG. 3, that is, in accepting,at the input of the remanence memory, the information (identification ofthe authorized radar) contained in the mosaic map for each pixel. Thecontent of the memory 2 then takes this parameter into account, and theinformation at the output of this memory is a function, at one and thesame time, of the two input video signals, the identification of theradar giving the video signal and the identification of the authorizedsignal.

This embodiment enables the use of IDCs comprising a block memory, withthe advantages inherent in it. Furthermore, should the block memory havea size smaller than that of the image memory, this embodiment has theadvantage, as compared with that of FIG. 3, of duplicating only theblock memories and not the image memory.

FIG. 7 represents a fourth embodiment of the mosaic according to theinvention, also in the case of IDCs provided with block memories.

In this embodiment, the system further has, for each of the radars, amemory known as a zone memory, referenced 75 and 75a respectively. Inone IDC, a memory such as this is used when it is sought to form"inserts" on the screen. It is recalled that the term "insert" isdefined as a part of the radar cover zone belonging or not belonging tothe image displayed on the screen, which is enlarged with respect tothis image. This possibility is, for example, used when the operatorseeks to examine a particular detail.

The zone memory (75, 75a), in this case receives the coordinates of thereading block, provided by the conversion set (3, 3a), and it containsthe indication that this block belongs or does not belong to the imageto be displayed. Its content is, for example, controlled (through theradar processor) by the operator (arrow 750). It accordingly gives theblock memory an authorization or non-authorization for reading.

In the system of FIG. 7, the content of the zone memory is modified soas to further comprise the indications previously contained in themosaic maps; the reading authorization then depends not only on theoperator's wish to have an "insert" but also on the mosaic map.

As in the previous embodiment, the system has an arbitrator circuit 73which authorizes the alternate reading of the memory blocks 8 and 8a:consequently, the authorization for reading, coming from the zonememories (75, 75a) is transmitted to the blocks memory through an ANDgate (76, 76a).

The advantage of this embodiment is that all that is sent to theremanence set 2 are the useful parts of the images of the two radars,i.e. the parts effectively used for the formation of the displayedmosaic. As a result, the access bus to the set 2 is half as utilized asin the case of FIG. 5, where the totality of the video signal of the tworadars is transmitted to the remanence set.

The above-described invention has been described, of course, by way of anon-restrictive example and it is thus, for example, that the differentembodiments described for a mosaic with two radars can be extended to amosaic with N radars.

We claim:
 1. Method for the display of several radar images as a singleresultant image, as a mosaic image of said radar images, each of theradar images being provided by a different radar in the form of analogvideo signals and polar coordinates of a respective radar,comprising:digitizing the video signal images of the radars: convertingthe polar coordinates associated with the video signals into Cartesiancoordinates; memorizing the digitized video signal images and Cartesiancoordinates; and, mutually excluding parts of said radar imagescomprising for each of the memorized images, transmitting a validatedimage, the pixels of which are validated by logic means for validatingeach pixel of each of the memorized images in response to validationdata provided by a memory containing a mosaic map, said data identifyingsaid pixel as belonging to the mosaic image to be displayed, anddisplaying the validated image pixels in a television mode display. 2.Method according to claim 1 further comprising for each of the images, aremanence step for varying the pixel values of the memorized image dataover time, and summing the validated images for display.
 3. Methodaccording to claim 1 further comprising:alternating transmission of thedifferent memorized images; memorizing for a second time the imagestransmitted; providing remanence to the image that has been memorizedthe second time, whereby said image is artificially aged, and duringwhich the mutual exclusion is carried out; and, displaying in saidtelevision mode the image memorized for a second time.
 4. Methodaccording to claim 1, further comprising for each of the images,following the step of mutual exclusion, the following steps:alternatingtransmission of the different images memorized and validated; memorizingfor a second time the images transmitted; and, displaying in televisionmode the image memorized for a second time.
 5. Apparatus for producing amosaic image from two or more radars observing the same geographicalsector comprising:means for digitizing each of the video signalsprovided by each radar to provide image pixels; means for convertingcoordinate data from each radar to Cartesian coordinates; a first memorymeans for memorizing the digitized image pixels and Cartesiancoordinates of said two radars, connected to the means for digitization,and means for conversion of coordinates; a second memory meanscontaining a mosaic map of validation information, for identifying eachpixel of the two or more images to be displayed; logic means forvalidating the pixels of each image connected to the second mosaic mapmemory; and, means to display the validated image pixels.
 6. Apparatusaccording to claim 5 wherein said logic means of validation is connectedto first and second memories comprising said first memory meanscontaining each of the radar images, the device further comprising meansfor summing the validated image pixels.
 7. Apparatus according to claim5 comprising means for providing for remanence of the memorized image,connected to the first memory and connected to the second memory, andmeans for summing the validated image pixels.
 8. Apparatus according toclaim 5, further comprising:arbitrator means connected to the firstmemory means and providing for an alternating transmission of thememorized images in the first memory means; a third memory providing formemorizing the image transmitted by the first memory means; and, meansproviding for the remanence of the image of the third memory. 9.Apparatus according to claim 5 further comprising:arbitrator meansconnected to the first memory means and providing for an alternatingtransmission of the images memorized in the first memory means; a thirdmemory providing for a second memorization of the image transmitted bythe first memory means, and connected to said means to display fordisplaying said memorized image; and, means providing for the remanenceof the image memorized in the third image memory.